A 6.25 ns random access 0.25 μm embedded DRAM

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 237-240

  DeMone, P ^a   Dunn, M ^a   Haerle, D ^a   Kim, J K ^a   Macdonald, D ^a   Nyasulu, P ^a   Perry, D ^a   Smith, S ^a   Wojcicki, T ^a   Zhang, Z ^a  

^a MOSAID Technologies Inc   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER ARCHITECTURE; COMPUTER CONTROL SYSTEMS; COMPUTER SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; SIGNAL PROCESSING;

NETWORKING APPLICATIONS;

EMBEDDED SYSTEMS;

EID: 0034784948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A multimedia 32b RISC microprocessor with 16Mb DRAM
2. 2RAM)
3. A 4.5 megabit, 560 MHz, 4.5 Gbyte/s high bandwidth SRAM
4. 64 Mb 6.8 ns random row access DRAM macro for ASICs
5. MoSys explains IT-SRAM technology