Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 159-164

  Diril, Abdulkadir U ^a   Dhillon, Yuvraj S ^a   Chatterjee, Abhijit ^a   Singh, Adit D ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEVEL SHIFTERS; LOGIC OPERATION; POWER CONSUMPTION; VOLTAGE GATES;

ELECTRIC POTENTIAL; GATES (TRANSISTOR); LOGIC PROGRAMMING;

CMOS INTEGRATED CIRCUITS;

EID: 27944433309     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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