A new analytical delay and noise model for on-chip RLC interconnect

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 823-826

  Cao, Y ^a   Huang, X ^a   Sylvester, D ^a   Chang, N ^a   Hu, C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC DELAY LINES; ELECTRIC WAVEFORMS; MATHEMATICAL MODELS; SECOND HARMONIC GENERATION; SPURIOUS SIGNAL NOISE; WAVEFORM ANALYSIS;

ON-CHIP INTERCONNECTS;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 0034449490     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. An analytical delay model for RLC interconnects
2. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
3. Compact distributed RLC models for multilevel interconnect networks
4. An efficient inductance modeling for on-chip interconnects