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Volumn 3659, Issue , 2005, Pages 354-365

Prototype IC with WDDL and differential routing - DPA resistance assessment

Author keywords

Countermeasure; Differential power analysis (DPA); Differential routing; Dual rail with precharge; Parasitic capacitance matching; Side channel attack (SCA); Wave dynamic differential logic (WDDL)

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; NUMBER THEORY; ROUTERS; SECURITY OF DATA;

EID: 27244438768     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11545262_26     Document Type: Conference Paper
Times cited : (132)

References (13)
  • 2
    • 84944319704 scopus 로고    scopus 로고
    • Statistics and secret leakage
    • Financial Cryptography (FC 2000), February
    • J. Coron, P. Kocher, and D. Naccache, "Statistics and Secret Leakage", Financial Cryptography (FC 2000), Lecture Notes in Computer Science, vol. 1962, pp. 157-173, February 2000.
    • (2000) Lecture Notes in Computer Science , vol.1962 , pp. 157-173
    • Coron, J.1    Kocher, P.2    Naccache, D.3
  • 3
    • 35248826454 scopus 로고    scopus 로고
    • Security evaluation of asynchronous circuits
    • Cryptographic Hardware and Embedded Systems (CHES 2003), September
    • J. Fournier, S. Moore, H. Li, R. Mullins and G. Taylor, "Security Evaluation of Asynchronous Circuits," Cryptographic Hardware and Embedded Systems (CHES 2003), Lecture Notes in Computer Science, vol. 2779, pp. 137-151, September 2003.
    • (2003) Lecture Notes in Computer Science , vol.2779 , pp. 137-151
    • Fournier, J.1    Moore, S.2    Li, H.3    Mullins, R.4    Taylor, G.5
  • 4
    • 29244432229 scopus 로고    scopus 로고
    • A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
    • accepted at April
    • Hodjat, D. Hwang, B. Lai, K. Tin, and I. Verbauwhede "A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-μm CMOS Technology", accepted at Great Lakes Symposium on VLSI (GLSVLSI 2005), April 2005.
    • (2005) Great Lakes Symposium on VLSI (GLSVLSI 2005)
    • Hwang, H.D.1    Lai, B.2    Tin, K.3    Verbauwhede, I.4
  • 10
    • 27244437234 scopus 로고    scopus 로고
    • Tektronix, CT1 current probe, http://www.tek.com/site/ps/60-12572/pdfs/ 60W_l 2572.pdf.
    • CT1 Current Probe
  • 13
    • 3042604811 scopus 로고    scopus 로고
    • A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
    • February
    • K. Tiri, and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", Design, Automation and Test in Europe Conference (DATE 2004), pp. 246-251, February 2004.
    • (2004) Design, Automation and Test in Europe Conference (DATE 2004) , pp. 246-251
    • Tiri, K.1    Verbauwhede, I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.