-
2
-
-
84944319704
-
Statistics and secret leakage
-
Financial Cryptography (FC 2000), February
-
J. Coron, P. Kocher, and D. Naccache, "Statistics and Secret Leakage", Financial Cryptography (FC 2000), Lecture Notes in Computer Science, vol. 1962, pp. 157-173, February 2000.
-
(2000)
Lecture Notes in Computer Science
, vol.1962
, pp. 157-173
-
-
Coron, J.1
Kocher, P.2
Naccache, D.3
-
3
-
-
35248826454
-
Security evaluation of asynchronous circuits
-
Cryptographic Hardware and Embedded Systems (CHES 2003), September
-
J. Fournier, S. Moore, H. Li, R. Mullins and G. Taylor, "Security Evaluation of Asynchronous Circuits," Cryptographic Hardware and Embedded Systems (CHES 2003), Lecture Notes in Computer Science, vol. 2779, pp. 137-151, September 2003.
-
(2003)
Lecture Notes in Computer Science
, vol.2779
, pp. 137-151
-
-
Fournier, J.1
Moore, S.2
Li, H.3
Mullins, R.4
Taylor, G.5
-
4
-
-
29244432229
-
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
-
accepted at April
-
Hodjat, D. Hwang, B. Lai, K. Tin, and I. Verbauwhede "A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-μm CMOS Technology", accepted at Great Lakes Symposium on VLSI (GLSVLSI 2005), April 2005.
-
(2005)
Great Lakes Symposium on VLSI (GLSVLSI 2005)
-
-
Hwang, H.D.1
Lai, B.2
Tin, K.3
Verbauwhede, I.4
-
5
-
-
0041589398
-
Design flow for HW/SW acceleration transparency in the ThumbPod secure embedded system
-
June
-
D. Hwang, P. Schaumont, Y. Fan, A. Hodjat, B. Lai, K. Sakiyama, S. Yang, and I. Verbauwhede, "Design flow for HW/SW acceleration transparency in the ThumbPod secure embedded system", 40th Design Automation Conference (DAC 2003), pp. 60-65, June 2003.
-
(2003)
40th Design Automation Conference (DAC 2003)
, pp. 60-65
-
-
Hwang, D.1
Schaumont, P.2
Fan, Y.3
Hodjat, A.4
Lai, B.5
Sakiyama, K.6
Yang, S.7
Verbauwhede, I.8
-
7
-
-
24144459808
-
Side-channel leakage of masked CMOS gates
-
February
-
S. Mangard, T. Popp, and B. Gammel, "Side-Channel Leakage of Masked CMOS Gates", Cryptographers' Track - RSA Conference (CT-RSA 2005), pp. 351-365, February 2005.
-
(2005)
Cryptographers' Track - RSA Conference (CT-RSA 2005)
, pp. 351-365
-
-
Mangard, S.1
Popp, T.2
Gammel, B.3
-
8
-
-
0041325255
-
Balanced self-checking asynchronous logic for smart card applications
-
S. Moore, R. Anderson, R. Mullins, and G. Taylor, "Balanced Self-Checking Asynchronous Logic for Smart Card Applications," Journal of Microprocessors and Microsystems, vol. 27, pp. 421-430, 2003.
-
(2003)
Journal of Microprocessors and Microsystems
, vol.27
, pp. 421-430
-
-
Moore, S.1
Anderson, R.2
Mullins, R.3
Taylor, G.4
-
9
-
-
17644372417
-
Towards an AES crypto-chip resistant to differential power analysis
-
September
-
N. Pramstaller, F. Gürkaynak, S. Häne, H. Kaeslin, N. Felber, and W. Fichtner, "Towards an AES Crypto-chip Resistant to Differential Power Analysis", 30th European Solid-State Circuits Conference (ESSCIRC 2004), pp. 307-310, September 2004.
-
(2004)
30th European Solid-state Circuits Conference (ESSCIRC 2004)
, pp. 307-310
-
-
Pramstaller, N.1
Gürkaynak, F.2
Häne, S.3
Kaeslin, H.4
Felber, N.5
Fichtner, W.6
-
10
-
-
27244437234
-
-
Tektronix, CT1 current probe, http://www.tek.com/site/ps/60-12572/pdfs/ 60W_l 2572.pdf.
-
CT1 Current Probe
-
-
-
13
-
-
3042604811
-
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
-
February
-
K. Tiri, and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation", Design, Automation and Test in Europe Conference (DATE 2004), pp. 246-251, February 2004.
-
(2004)
Design, Automation and Test in Europe Conference (DATE 2004)
, pp. 246-251
-
-
Tiri, K.1
Verbauwhede, I.2
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