A VLSI design flow for secure side-channel attack resistant ICs

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn 2005, Issue , 2005, Pages 58-63

  Tiri, Kris ^a   Verbauwhede, Ingrid ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DES ALGORITHM; DESIGN FLOW; SIDE-CHANNEL ATTACK (SCA); VHDL;

ALGORITHMS; ARCHITECTURAL DESIGN; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL LIBRARIES; ITERATIVE METHODS; SECURITY SYSTEMS; VLSI CIRCUITS;

INTEGRATED CIRCUITS;

EID: 28444486136     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.44     Document Type: Conference Paper

References (15)

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