메뉴 건너뛰기




Volumn , Issue , 2004, Pages 315-320

Evaluation of memory built-in self repair techniques for high defect density technologies

Author keywords

[No Author keywords available]

Indexed keywords

BUILT IN SELF REPAIR (BISR); BUILT IN SELF TESTS (BIST); EMBEDDED MEMORIES;

EID: 2642559540     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2004.1276581     Document Type: Conference Paper
Times cited : (6)

References (13)
  • 1
    • 0032510985 scopus 로고    scopus 로고
    • A defect-tolerant computer architecture: Opportunities for nanotechnology
    • June 12
    • Heath J.R., Kuekes P.J., Snider G.S., Stanley Williams R., "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology", SCIENCE, Vol. 280, June 12, 1998
    • (1998) Science , vol.280
    • Heath, J.R.1    Kuekes, P.J.2    Snider, G.S.3    Stanley Williams, R.4
  • 2
    • 0036443181 scopus 로고    scopus 로고
    • Embedded memory test & repair: Infrastructure IP for SOC yield
    • Zorian Y., "Embedded Memory Test & Repair: Infrastructure IP for SOC Yield", 2002 IEEE Int'l Test Conf.
    • 2002 IEEE Int'l Test Conf.
    • Zorian, Y.1
  • 4
    • 0026955424 scopus 로고
    • A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
    • Nov.
    • Tanabe A. et al " A 30-ns 64-Mb DRAM with Built-in Self-test and Self-Repair Function", IEEE Journal Solid State Circuits, pp. 1525-1533, Vol 27, No 11, Nov. 1992.
    • (1992) IEEE Journal Solid State Circuits , vol.27 , Issue.11 , pp. 1525-1533
    • Tanabe, A.1
  • 6
    • 84960439799 scopus 로고    scopus 로고
    • A family of self-repair SRAM cores
    • 2000 IEEE International Test Conference. 2000, July 3-5
    • Benso A. et al "A Family of Self-Repair SRAM Cores", 2000 IEEE International Test Conference. 2000 In Proc. IEEE International On-Line Testing Workshop, July 3-5, 2000.
    • (2000) Proc. IEEE International On-line Testing Workshop
    • Benso, A.1
  • 8
    • 84964929905 scopus 로고    scopus 로고
    • A BISR (buil-in self-repair) circuit for embedded memory with multiple redundancies
    • Oct. 26-27, Seoul, Korea
    • Kim H. C., Yi D.S., Park J.Y., Cho C.H., "A BISR (Buil-In Self-Repair) circuit for embedded memory with multiple redundancies", 1999 IEEE International Conference on VLSI and CAD, Oct. 26-27, 1999, Seoul, Korea, pp 602-605
    • (1999) 1999 IEEE International Conference on VLSI and CAD , pp. 602-605
    • Kim, H.C.1    Yi, D.S.2    Park, J.Y.3    Cho, C.H.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.