Meeting manufacturing metrology challenges at 90 nm and beyond

MICRO

Volumn 23, Issue 7, 2005, Pages 31-40

  Bunday, Benjamin ^a   Godwin, Milton ^a   Lipscomb, Pete ^a   Patel, Dilip ^a   Bishop, Michael ^a,b   Allgair, John ^b   Diebold, Alain C ^b  

^a SEMATECH   (United States)

^b Sematech ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERNATIONAL SEMATECH MANUFACTURING INITIATIVE (ISMI); LITHOGRAPHY METROLOGY; OPTICS IMPROVEMENTS; WAFER INSPECTION;

DEFECTS; LITHOGRAPHY; MANUFACTURE;

MEASUREMENT THEORY;

EID: 25444496725     PISSN: 10810595     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (14)

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3. B Bunday et al., Unified Advanced CD-SEM Specification for Sub-90 nm Technology, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2004); available from Internet: www.sematech.org.
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8. C Tabery et al., "Design-Based Metrology: Advanced Automation for CD-SEM Recipe Generation," in Proceedings of SPIE, vol. 5752 (Bellingham, WA: SPIE, 2005), 527-535.
9. B Bunday et al., Unified Advanced Optical Critical Dimension (OCD) Scatterometry Specification for Sub-90 nm Node Technology, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2004); available from Internet: www.sematech.org.
10. M Bishop, Feasibility Study of the WIS/TIS Module, Sematech Technology Transfer Report to Members (Austin, TX: Sematech, 2002).
11. M Adel et al., "Characterization of Overlay Mark Fidelity," in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 437-444.
12. WJ Trybula, "Challenges of Image Placement and Overlay at the 90-nm and 65-nm Nodes," in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 286-292.
13. P Leray, D Laidler, and I Pollentier, "Comparison of Pattern Placement Errors as Measured Using Traditional Overlay Targets and Design Rule Structures," in Proceedings of SPIE, vol. 5038 (Bellingham, WA: SPIE, 2003), 49-60.
14. JA Allgair and KM Monahan, "Microeconomics of Overlay Control at the 65 nm Technology Node," in Proceedings of the IEEE International Symposium on Semiconductor Manufacturing (Piscataway, NJ: IEEE, 2003), 103-106.