Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 531-536

  Iima, Tomofumi ^b,c   Mizuno, Masayuki ^a,b,d,e   Horiuchi, Tadahiko ^b,f,g,h,i   Yamashina, Masakazu ^a,b,e,j,k  

^a IEEE

^b NEC CORPORATION   (Japan)

^c TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

^d OSAKA UNIVERSITY   (Japan)

^e TOHOKU UNIVERSITY

^f KYOTO UNIVERSITY   (Japan)

^g TOHOKU UNIVERSITY   (Japan)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^j TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^k STANFORD UNIVERSITY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; ELECTRIC RESISTANCE; LSI CIRCUITS; TELECOMMUNICATION; TRIGGER CIRCUITS; ULSI CIRCUITS;

BIDIRECTIONAL SIGNAL COMMUNICATION; CAPACITANCE COUPLING IMMUNE; RESISTIVE INTERCONNECT SIGNALS; TRANSIENT SENSITIVE ACCELERATOR CIRCUIT; TRANSIENT SENSITIVE TRIGGER CIRCUIT;

DELAY CIRCUITS;

EID: 0030121769     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499729     Document Type: Article

References (4)

1. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
2. T. Sakurai and K. Tamara, "Simple formulas for two- and three-dimensional capacitances," IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 183-185, Feb. 1983.
3. T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SC-18, no. 4, pp. 418-425, Aug. 1983.
4. T. Iima, M. Mizuno, T. Horiuchi, and M. Yamashina, "Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI," in Symp. on VLSI Circuits Dig. of Tech. Papers, 1995, pp. 31-32.