Applications of CPL™ mask technology for sub-65nm gate imaging

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5754, Issue PART 3, 2005, Pages 1459-1468

  Litt, Lloyd C ^a   Conley, Will ^a   Wu, Wei ^a   Peters, Richie ^a   Parker, Colita ^a   Cobb, Jonathan ^a   Kasprowicz, Bryan S ^b   Van Broeke, Doug Den ^c   Park, J C ^c   Karur Shanmugam, Ramkumar ^d  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b PHOTRONICS INC   (United States)

^c ASML US Inc   (United States)

^d UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

Chromeless; Lithography; Phase; Resolution enhancement techniques; RET

Indexed keywords

COLORING; GATES (TRANSISTOR); IMAGING TECHNIQUES; LIGHTING; LITHOGRAPHY; LOGIC DESIGN; PHASE SHIFT;

CHROMELESS; CRITICAL DIMENSION (CD); PHASE; RESOLUTION ENHANCEMENT TECHNIQUES (RET);

MASKS;

EID: 25144520431     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.600912     Document Type: Conference Paper

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