A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 9, 2005, Pages 1940-1947

  Coban, Abdulkerim L ^a   Koroglu, Mustafa H ^a   Ahmed, Kashif A ^a  

^a Mindspeed Technologies   (United States)

Author keywords

Chip to chip communication; Clock and data recovery (CDR); Delay locked loop (DLL); Phase locked loop (PLL); Serial communication; Transceivers

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; JITTER; PHASE LOCKED LOOPS;

CHIP-TO-CHIP COMMUNICATION; CLOCK AND DATA RECOVERY (CDR); DELAY-LOCKED LOOP (DLL); SERIAL COMMUNICATION;

TRANSCEIVERS;

EID: 25144466873     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848142     Document Type: Conference Paper

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