A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 9, 2004, Pages 1553-1561

  Farjad Rad, Ramin ^a,b   Nguyen, Anhtuyet ^a,b   Tran, James M ^a,b   Greer, Trey ^a,b   Poulton, John ^a,b   Dally, William J ^c   Edmondson, John H ^a,d   Senthinathan, Ramesh ^a,e   Rathi, Rohit ^a,f   Lee, M J Edward ^a,f   Ng, Hiok Tiaq ^a,f  

^a Velio Communications Inc   (United States)

^b RAMBUS INC   (United States)

^c STANFORD UNIVERSITY   (United States)

^d NVIDIA   (United States)

^e ADVANCED MICRO DEVICES   (United States)

^f ATi Research Silicon Valley Inc   (United States)

Author keywords

Clock and data recovery (CDR); Clock multiplication; Frequency tracking acquisition; High speed transceivers; Injection locking; Jitter filtering; Multiplying DLL; Phase interpolation

Indexed keywords

CLOCK AND DATA RECOVERY (CDR) CIRCUITS; FREQUENCY TRACKING; INJECTION LOCKING; PHASE INTERPOLATION;

BANDWIDTH; ELECTRIC POTENTIAL; JITTER; MICROPROCESSOR CHIPS; MULTIPLEXING; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; THERMAL EFFECTS; TRANSCEIVERS; VOLTAGE CONTROL;

CMOS INTEGRATED CIRCUITS;

EID: 4444270147     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831457     Document Type: Conference Paper

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