Reducing energy consumption by dynamic copying of instructions onto onchip memory

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2002, Pages 213-218

  Steinke, Stefan ^a   Grunwald, Nils ^a   Wehmeyer, Lars ^a   Banakar, Rajeshwari ^b   Balakrishnan, M ^b   Marwedel, Peter ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Energy optimization; Onchip memory

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; INTEGER PROGRAMMING; LINEAR PROGRAMMING; PERFORMANCE;

INTEGER LINEAR PROGRAMMING; ONCHIP MEMORY;

EMBEDDED SYSTEMS;

EID: 0036953785     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581199.581247     Document Type: Conference Paper

References (17)

1. ARM, Advanced RISC Machines Ltd. www.arm.com
2. R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. Comparison of cache- and scratch-pad-based memory systems with respect to performance, area and energy consumption. Technical Report 762, University of Dortmund, Sep. 2001.
3. R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. Scratchpad Memory: A Design Alternative for Cache On-chip memory in Embedded Systems. In Proc. of the 10th International Workshop on Hardware/Software Codesign, CODES, Estes Park (Colorado), May 2002.
4. L. Benini, A. Macii, E. Macii, and M. Ponicino. Synthesis of application-specific memories for power optimization in embedded systems. In Proc., of the 37th Design Automation Conference, 300-303, Los Angeles, CA, Jun. 2000.
5. encc. University of Dortmund, Computer Science Dep., ls12-www.cs.uni-dortmund.de/research/encc.
6. Intel. Mobile Power Guidelines 2000. Technical Report 1.0, Intel Corporation, Dec. 1998.
7. T. Ishihara and H. Yasuura. A power reduction technique with object code merging for application specific embedded processors. In Proc. of the Design, Automation and Test in Europe Conference, pages 617-623, Paris, Mar. 2000.
8. M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. Dynamic Management of Scratch-Pad Memory Space. In Proc. of 38th Design Automation Conference, pages 690-695, Las Vegas, NV, Jun. 2001.
9. M. Kandemir, I. M. Vijakrishnan, N., and W. Ye. Influence of compiler optimizations on system power. In Proc. of the 37th Design Automation Conference, pages 304-307, Los Angeles, CA, Jun. 2000.
10. G. L. Nehmhauser and L. A. Wolsey. Integer and Combinatorial Optimization. John Wiley and Sons, New York, NY, 1988.
11. P. R. Panda, N. D. Dutt, and A. Nicolau. Memory Issues in Embedded Systems-On-Chip. Kluwer Academic Publishers, Norwell, MA, 1999.
12. T. Simunic, L. Benini, and G. De Micheli. Cycle-accurate simulation of energy consumption in embedded systems. In Proc. of the 36th Design Automation Conference, New Orleans, LA, Jun. 1999.
13. J. Sjödin, B. Fröderberg, and T. Lindgren. Allocation of Global Data Objects in On-Chip RAM. In Proc. Workshop on Compiler and Architectural Support for Embedded Computer Systems, Washington DC, Dec. 1998. ACM.
14. S. Steinke, M. Knauer, L. Wehmeyer, and P. Marwedel. An accurate and fine grain instruction-level energy model supporting software optimizations. In PATMOS 01, Yverdon-Les-Bains, Switzerland, Sep. 2001.
15. S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel. Assigning program and data objects to scratchpad for energy reduction. In Proc. of DATE, Paris, France, Mar. 2002.
16. V. Tiwari, S. Malik, and A. Wolfe, Compilation techniques for low energy: An overview. In Proceedings of the IEEE Symposium on Low Power Electronics, San Diego, CA, Oct. 1994.
17. S. J. E. Wilton and N. P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31 (5): 677-688, May 1996.