An efficient merging scheme for prescribed skew clock routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 6, 2005, Pages 750-754

  Chaturvedi, Rishi ^a   Hu, Jiang ^b  

^a ANALOG DEVICES INC   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Clocks; Design automation; Very large scale integration

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); CAPACITANCE; CLOCKS; COMPUTATIONAL COMPLEXITY; DATA TRANSFER; ELECTRIC POWER UTILIZATION; METRIC SYSTEM; ROUTERS;

BOTTOM-UP FASHION; DESIGN AUTOMATION; SKEW CLOCK ROUTING; VERY LARGE-SCALE INTEGRATION;

VLSI CIRCUITS;

EID: 23744508760     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.848821     Document Type: Article

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