Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

Nuclear Instruments and Methods in Physics Research, Section B: Beam Interactions with Materials and Atoms

Volumn 237, Issue 1-2, 2005, Pages 126-130

  Walther, S ^a   Lenoble, D ^b   Lallement, F ^b   Grouillet, A ^b   Erokhin, Y ^a   Singh, V ^a   Testoni, A ^a  

^a VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); ION IMPLANTATION; PLASMA APPLICATIONS; SEMICONDUCTOR DOPING;

BEAMLINE IMPLANTS; OFFSET SPACERS; PLASMA DOPING; SOURCE AND DRAIN EXTENSIONS (SDE);

CMOS INTEGRATED CIRCUITS;

EID: 23444452934     PISSN: 0168583X     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.nimb.2005.04.087     Document Type: Conference Paper

References (11)

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