Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 381-391

  Huang, Chung Yang ^a,b,c   Cheng, Kwang Ting ^a,b  

^a IEEE   (United States)

^b University of California   (United States)

^c Verplex Systems Inc   (United States)

Author keywords

ATPG; Formal verification; Model checking; RTL

Indexed keywords

ASSERTION PROPERTY CHECKING; AUTOMATIC TEST PATTERN GENERATION; FORMAL VERIFICATION; MODULAR ARITHMETIC CONSTRAINT-SOLVING TECHNIQUES;

ALGORITHMS; AUTOMATIC TESTING; COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; MATRIX ALGEBRA; THEOREM PROVING;

DESIGN FOR TESTABILITY;

EID: 0035272705     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913756     Document Type: Article

References (24)

1. Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming
2. The CLP(R) language and system
3. Validation tools for complex digital designs
4. Design verification and reachability analysis using algebraic manipulation
5. Functional vector generation for HDL models using linear programming and 3-satisfiability
6. Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
7. Automatic generation of functional vectors using the extended finite-state machine model
8. A new extended finite-state machine (EFSM) model for RTL design verification
9. Online minimization of transition systems
10. Synthesis of synchronization skeletons for branching time temporal logic
11. Murphi description language and verifier
12. Approximate reachability don't cares for CTL model checking
13. The SMV System
14. VIS: A system for verification and synthesis
15. Graph-based algorithms for Boolean function manipulation
16. Symbolic model checking using SAT procedures instead of BDDs
17. A temporal logic of concurrent programs
18. SCOAP: Sandia controllability/observability analysis problem
19. On testability analysis of combinational networks