Practical use of sequential ATPG for model checking: Going the extra mile does pay off

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 39-44

  Hsiao, M ^a   Jain, J ^b  

^a Virginia Polytechnic Institute and State University   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; EXCITED STATES; MICROPROCESSOR CHIPS;

PRACTICAL USE; SEQUENTIAL ATPG; STATE INFORMATION; STATE SPACE INFORMATION;

MODEL CHECKING;

EID: 2342667434     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972805     Document Type: Conference Paper

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