Fast algorithm for optimal wire-sizing under Elmore delay model

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 412-415

  Chen, Chung Ping ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CIRCUIT THEORY; CONVERGENCE OF NUMERICAL METHODS; EFFICIENCY; ELECTRIC RESISTANCE; ELECTRIC WIRE; ESTIMATION; ITERATIVE METHODS; MATHEMATICAL MODELS; OPTIMIZATION; TREES (MATHEMATICS);

ELMORE DELAY MODEL; ITERATIVE ALGORITHM; NON NEGATIVE WEIGHTS; OPTIMAL WIRE SIZING; ROUTING TREE; WIRE SEGMENT PROBLEM;

ALGORITHMS;

EID: 0029699424     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)