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Volumn 40, Issue 7, 2005, Pages 1583-1587

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

Author keywords

Decision circuit; HBT; InP; Optical communications

Indexed keywords

ALGORITHMS; ELECTRON TRANSITIONS; FLIP FLOP CIRCUITS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; OPTICAL COMMUNICATION; RESISTORS;

EID: 22544470923     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.847521     Document Type: Conference Paper
Times cited : (9)

References (11)
  • 3
    • 0029221237 scopus 로고
    • Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops
    • Jan.
    • K. Ishii, H. Ichino, M. Togashi, Y. Kobayashi, and C. Yamaguchi, "Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops," IEEE J. Solid-State Circuits, vol. 30, no. 1, pp. 19-24, Jan. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , Issue.1 , pp. 19-24
    • Ishii, K.1    Ichino, H.2    Togashi, M.3    Kobayashi, Y.4    Yamaguchi, C.5
  • 4
    • 0022864857 scopus 로고
    • An 8-bit 250 megasample per second analog-to-digital converter: Operation without a sample and hold
    • Dec.
    • B. Peetz, B. D. Hamilton, and J. Kang, "An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold," IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 997-1002, Dec. 1986.
    • (1986) IEEE J. Solid-state Circuits , vol.SC-21 , Issue.6 , pp. 997-1002
    • Peetz, B.1    Hamilton, B.D.2    Kang, J.3
  • 7
    • 0037004969 scopus 로고    scopus 로고
    • max InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base
    • Dec.
    • max InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base," IEEE Electron Device Lett., vol. 23, no. 12, pp. 694-696, Dec. 2002.
    • (2002) IEEE Electron Device Lett. , vol.23 , Issue.12 , pp. 694-696
    • Ida, M.1    Kurishima, K.2    Watanabe, N.3
  • 9
    • 0037030552 scopus 로고    scopus 로고
    • High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs
    • K. Ishii, H. Nosaka, M. Ida, K. Kurishima, T. Enoki, T. Shibata, and E. Sano, "High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs," Electron. Lett., vol. 38, pp. 557-558, 2002.
    • (2002) Electron. Lett. , vol.38 , pp. 557-558
    • Ishii, K.1    Nosaka, H.2    Ida, M.3    Kurishima, K.4    Enoki, T.5    Shibata, T.6    Sano, E.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.