4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

IEEE Transactions on Microwave Theory and Techniques

Volumn 51, Issue 11, 2003, Pages 2181-2187

  Ishii, Kiyoshi ^a   Nosaka, Hideyuki ^a   Ida, Minoru ^a   Kurishima, Kenji ^a   Yamahata, Shoji ^a   Enoki, Takatomo ^a   Shibata, Tsugumichi ^a   Sano, Eiichi ^a,b  

^a NTT CORPORATION   (Japan)

^b HOKKAIDO UNIVERSITY   (Japan)

Author keywords

Clock and data recovery (CDR); Demultiplexer (DEMUX); HBT; InP; Integrated circuit (IC) design; Multiplexer (MUX); Optical communications

Indexed keywords

COMPUTER ARCHITECTURE; CURRENT DENSITY; DEMULTIPLEXING; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTICAL COMMUNICATION;

CLOCK AND DATA RECOVERY; DEMULTIPLEXER; SELECTOR;

MULTIPLYING CIRCUITS;

EID: 0242720719     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2003.818582     Document Type: Article

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