Low-Error Carry-Free Fixed-Width Multipliers With Low-Cost Compensation Circuits

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 52, Issue 6, 2005, Pages 299-303

  Juang, Tso Bing ^a   Hsiao, Shen Fu ^b  

^a Ta Jen Institute of Technology   (Taiwan)

^b NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

Fixed width multipliers; modified booth encoding (MBE); redundant number representations

Indexed keywords

COMPUTATION THEORY; COSINE TRANSFORMS; ERROR COMPENSATION; IMAGE ANALYSIS; IMAGE CODING; IMAGE COMPRESSION; IMAGE QUALITY; INVERSE PROBLEMS; STATISTICAL METHODS;

BINARY SIGNED DIGIT-REPRESENTATION; FIXED WIDTH MULTIPLIERS; LOW-COMPENSATION CIRCUITS; MODIFIED BOOTH ENCODING (MBE); REDUNDANT NUMBER REPRESENTATIONS;

MULTIPLYING CIRCUITS;

EID: 22244483441     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.848956     Document Type: Article

References (10)

1. Y. C. Lim, “Single precision multiplier with reduced circuit complexity for signal processing applications,” IEEE Trans. Comp., vol. 41, no. 10, pp. 1333–1336, Oct. 1992.
2. M. J. Schutle and E. E. Swartzlander Jr., “Truncated multiplication with correction constant,” VLSI Signal Process., vol. 6, pp. 388–396, 1993.
3. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-efficient multipliers for digital signal processing applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 2, pp. 90–95, Feb. 1996.
4. J. M. Jou, S. R. Kuang, and R. D. Chen, “Design of low-error fixed-width multipliers for DSP applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 836–842, Jun. 1999.
5. L. D. Van, S. S. Wang, and W. S. Feng, “Design of the lower error fixed-width multiplier and its application,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 10, pp. 1112–1118, Oct. 2000.
6. S. J. Jou and H. H. Wang, “Fixed-width multiplier for DSP application,” in Proc. International Conf. Computer Design (ICCD), Sep. 2000, pp. 318–322.
7. K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parhi, “Design of low-error fixed-width modified booth multiplier,” IEEE Trans. VLSI Syst., vol. 12, no. 5, pp. 522–531, May 2004.
8. N. Besli and R. G. Deshmukh, “A novel redundant binary signed-digit (RBSD) Booth's encoding,” in Proc. IEEE Southeast Conf., 2002, pp. 426–431.
9. H. Makino, Y. Nakase, H. Suzuki, H. Morokina, H. Shinohara, and K. Mashiko, “An 8.8-ns 54x 54-bit multiplier with high speed redundant binary architecture,” IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 773–783, Jun. 1996.
10. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford, U.K.: Oxford Univ. Press, 2000, pp. 93–96.