An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 773-782

  Makino, Hiroshi ^b,c,d,e   Nakase, Yasunobu ^b,e,f   Suzuki, Hiroaki ^b,g,h   Morinaka, Hiroyuki ^b,d,i   Shinohara, Hirofumi ^b   Mashiko, Koichiro ^a,b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c KYOTO UNIVERSITY   (Japan)

^d System LSI Laboratory

^e TOHOKU UNIVERSITY

^f RITSUMEIKAN UNIVERSITY   (Japan)

^g OSAKA INSTITUTE OF TECHNOLOGY   (Japan)

^h Institute of Electrical Engineers of   (Japan)

ⁱ OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BINARY SEQUENCES; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; TREES (MATHEMATICS);

HIGH SPEED REDUNDANT BINARY ARCHITECTURE;

MULTIPLYING CIRCUITS;

EID: 0030169609     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509863     Document Type: Article

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