Improvement in reproducibility of multilayer and junction process for HTS SFQ circuits

IEEE Transactions on Applied Superconductivity

Volumn 15, Issue 2 PART I, 2005, Pages 153-156

  Wakana, Hironori ^a   Adachi, Seiji ^a   Kamitani, Ai ^a   Nakayama, Kouhei ^a   Ishimaru, Yoshihiro ^a   Oshikubo, Yasuo ^a   Tarutani, Yoshinobu ^a   Tanabe, Keiichi ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

High temperature superconductor; Josephson junction; Ramp edge structure; SFQ circuit

Indexed keywords

CERAMIC MATERIALS; FABRICATION; JOSEPHSON JUNCTION DEVICES; MAGNESIA; MAGNETRON SPUTTERING; MORPHOLOGY; MULTILAYERS; PEROVSKITE; SURFACE ROUGHNESS; THIN FILMS;

JUNCTION ARRAYS; MULTILAYER STRUCTURES; RAMP-EDGE STRUCTURE; SINGLE FLUX QUANTUM (SFQ) CIRCUIT;

HIGH TEMPERATURE SUPERCONDUCTORS;

EID: 22144452141     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849723     Document Type: Conference Paper

References (16)

1. c Josephson junctions," Appl. Phys. Lett., vol. 71, no. 17, pp. 2526-2528, Oct. 1997.
2. T. Satoh, M. Hidaka, and S. Tahara, "High-temperature superconducting edge-type Josephson junctions with modified interfaces," IEEE Trans. Appl. Supercond., vol. 9, pp. 3141-3144, Jun. 1999.
3. Y. Ishimaru, Y. Wu, O. Horibe, H. Tano, T. Suzuki, Y. Yoshida, M. Horibe, H. Wakana, S. Adachi, Y. Takahashi, Y. Oshikubo, H. Sugiyama, M. Iiyama, Y. Tarutani, and K. Tanabe, "Evaluation of fabrication process and barrier structure for interface-modified ramp-edge junctions," Physica C, vol. 378-381, pp. 1327-1333, 2002.
4. y, counter-electrode layer," Appl. Phys. Lett., vol. 79, pp. 4189-4191, Dec. 2001.
5. H. Wakana, S. Adachi, M. Horibe, Y. Ishimaru, O. Horibe, Y. Tarutani, and K. Tanabe, "Influence of counter-layer deposition condition on critical current spread in interface-modified ramp-edge junction arrays," Jpn. J. Appl. Phys., vol. 41, pp. L239-L242, Mar. 2002.
6. y, upper layers on electrical properties of interface-modified ramp-edge junction," Physica C, vol. 378-381, pp. 1353-1356, 2002.
7. H. Katsuno, S. Inoue, T. Nagano, and J. Yoshida, "Novel multilayer process for HTS SFQ circuit," IEEE Trans. Appl. Supercond., vol. 13, no. 2, pp. 809-812, Jun. 2003.
8. Y. Soutome, T. Fukazawa, K. Saitoh, A. Tsukamoto, and K. Takagi, "HTS surface-modified junctions with integrated ground-planes for SFQ circuits," IEICE Trans. Electronics, vol. E85-C, pp. 759-763, Mar. 2002.
9. H. Wakana, S. Adachi, H. Sugiyama, Y. Takahashi, T. Sugano, M. Horibe, Y. Ishimaru, Y. Tarutani, and K. Tanabe, "Ramp-edge junctions with interface-modified barriers fabricated on YBCO thick films," IEEE Trans. n Appl. Supercond., vol. 13, no. 2, pp. 595-598, Jun. 2003.
10. K. Nakayama, Y. Ishimaru, H. Wakana, S. Adachi, Y. Tarutani, and K. Tanabe, "Fabrication of high-quality multilayer structure for HTS-SFQ circuits using surface treatments," in ASC2004, 2EG09.
11. H. Wakana, S. Adachi, M. Horibe, Y. Ishimaru, Y. Oshikubo, Y. Tarutani, and K. Tanabe, "Development of two-step deposition process for interface-modified ramp-edge Josephson junction with low sheet inductance and small spread," Jpn. J. Appl. Phys., vol. 41, no. 12A, pp. L1366-L1369, Dec. 2002.
12. H. Wakana, S. Adachi, A. Kamitani, K. Nakayama, Y. Ishimaru, Y. Tarutani, and K. Tanabe, "Development of thin film multilayer structures with smooth surfaces for HTS SFQ circuits," IEICE Trans. Electronics, to be published.
13. c superconducting single-flux-quantum circuits," Supercond. Sci. Technol., vol. 16, pp. 1493-1496, Nov. 2003.
14. c multilayer technology," Appl. Phys. Lett., vol. 84, no. 14, pp. 2587-2589, Feb. 2004.
15. Y. Tarutani, Y. Ishimaru, H. Wakana, S. Adachi, K. Nakayama, Y. Oshikubo, O. Horibe, Y. Morimoto, and K. Tanabe, "New type of SFQ-dc converter for use in oxide circuits," Physica C, to be published.
16. Y. Tarutani, Y. Ishimaru, H. Wakana, S. Adachi, K. Nakayama, Y. Oshikubo, O. Horibe, and K. Tanabe, "Fabrication of oxide SFQ-circuit-elements including SFQ-dc converter," in ASC2004, 5EJ04.