Proposal of new HfSiON CMOS fabrication process (HAMDAMA) for low standby power device

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 95-98

  Aoyama, T ^a   Maeda, T ^a   Torii, K ^a   Yamashita, K ^a   Kobayashi, Y ^a   Kamiyama, S ^a   Miura, T ^a   Kitajima, H ^a   Arikado, T ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CURRENT VOLTAGE CHARACTERISTICS; DEPOSITION; ENERGY DISPERSIVE SPECTROSCOPY; FIELD EFFECT TRANSISTORS; HAFNIUM COMPOUNDS; ION IMPLANTATION; OXIDES; POLYSILICON; POWER SUPPLY CIRCUITS; RAPID THERMAL ANNEALING; X RAY DIFFRACTION ANALYSIS; CMOS INTEGRATED CIRCUITS; FABRICATION; HOLE MOBILITY; NICKEL COMPOUNDS; POLYCRYSTALLINE MATERIALS; SILICIDES;

DOPANT IMPLANTATION; HALF-MASKED DAMASCENE-LIKE FULL SILICIDATION (HAMDAMA); SHALLOW TRENCH ISOLATION (STI); SILICIDATION;

CMOS INTEGRATED CIRCUITS; HAFNIUM COMPOUNDS;

CMOS FABRICATION; CMOSFETS; DUAL GATES; FABRICATION PROCESS; FULL SILICIDATION; FUSI NISI; LOW STAND-BY POWER DEVICES; POLY-SI GATE PROCESS; SILICIDATION PROCESS;

EID: 21644482964     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. K. Sekine et al., "Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current," IEDM Tech. Dig. 2003, pp.103-106.
2. C. Hobbs et al., "Fermi level pinning at the polySi/metal oxide interface," Symp. VLSI Tech. 2003, pp.9-10.
3. Y. Tamura et al., "SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors," Symp. VLSI Tech. 2004, pp.210-211.
4. W. P. Maszara, Z. Krivokapic, P. King, J. -S. Goo and M. -R. Lin, "Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates," IEDM Tech. Dig. 2002, pp.367-370.
5. 2 based high-k gate dielectrics as a candidate for low power applications," Symp. VLSI Tech. 2004, pp. 190-191.
6. t with Hf-based gate stacks with poly-Si and FUSI gates," Symp. VLSI Tech. 2004, pp.44-45.
7. M. Qin, V. M. C. Poon and S. C. H. Ho, "Investigation of polycrystalline nickel silicide films as a gate material," J. Electrochem. Soc. Vol.148 (5), pp.G271-G274, May 2001.
8. T. Aoyama et al., "Nitrided hafnium silicate film formation by sequential process using a hot wall batch system and its application to MOS transistor," Mat. Res. Soc. Symp. Proc., vol.786, pp.273-278, 2004.
9. International Technology Roadmap for Semiconductors, 2003.