SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistors

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 210-211

  Tamura, Y ^a   Sasaki, T ^a   Izumi, N ^a   Ootsuka, F ^a   Yasuhira, M ^a   Hoshi, T ^a   Kume, S ^a   Amai, H ^a   Ida, T ^a   Aoyama, T ^a   Kamiyama, S ^a   Torii, K ^a   Kitajima, H ^a   Arikado, T ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

Author keywords

HfSiON; High k; SiN cap and Bias temperature

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; FERMI LEVEL; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; MOS DEVICES; SILICON COMPOUNDS; TEMPERATURE CONTROL; THICKNESS CONTROL;

BIAS TEMPERATURE; CAPPING; EQUIVALENT OXIDE THICKNESS (EOT); NITRIDATION;

TRANSISTORS;

EID: 4544250302     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345484     Document Type: Conference Paper

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