DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 3, 2004, Pages 245-254

  Li, Hai ^a   Bhunia, Swarup ^a   Chen, Yiran ^a   Roy, Kaushik ^a   Vijaykumar, T N ^a  

^a Purdue University   (United States)

Author keywords

Deterministic clock gating (DCG); Superscalar microarchitecture

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; LOGIC CIRCUITS; TREES (MATHEMATICS); TUNING; VLSI CIRCUITS;

DETERMINISTIC CLOCK-GATING (DCG); INSTRUCTION LEVEL PARALLELISM (ILP); PIPELINE BALANCING (PLB); SUPERSCALAR MICROARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 2142805953     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.824307     Document Type: Conference Paper

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