A Novel W/WNx/Dual-Gate CMOS Technology for Future High-Speed DRAM Having Enhanced Retention Time and Reliability

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 415-418

  Saino, K ^a   Kato, Y ^a   Kitamura, E ^a   Takaishi, Y ^a   Ando, M ^a   Taguwa, T ^a   Kanda, T ^a   Yamada, S ^a   Sekiguchi, T ^a  

^a Elpida Memory Inc   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC FIELDS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GATES (TRANSISTOR); HEAT TREATMENT; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); TRANSISTORS;

MEMORY CELL (MC) TRANSISTORS; RETENTION TIME; SELF-ALIGN CONTACT (SAC);

CMOS INTEGRATED CIRCUITS;

EID: 0842331355     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Hiura, A. Azuma, K. Nakajima, Y. Akasaka, K. Miyano, H. Nitta, A. Honjo, K. Tsuchida, Y. Toyoshima, K. Suguro and Y. Kohyama, "Integration Technology of Polymetal (W/WSiN/Poly-Si) Dual Gate CMOS for 1Gbit DRAMS and Beyond," IEDM Tech. Dig.,1998, pp. 389-392.
2. T. Hamamoto, S. Sugiura, S. Sawada, "On the retention time distribution of Dynamic Random Access Memory (DRAM)," IEEE Trans, on Electron Dev., Vol. 45, pp. 1300-1309, June 1998.
3. H. Kujirai, K. Ohyu, M. Moniwa, H. Kato, K. Nakai, H. Iwai, M. Nanba and A. Ogishima, "Data Retention Time in DRAM with WSix/P+ Poly-Si Gate NMOS Cell Transistors," IEDM Tech. Dig., 2001, pp. 395-398.
4. H. W. Seo, G Y. Jin, K. H. Yang, Y. J. Lee, J. H. Lee, D. H. Song, Y. C. Oh, J. Y. Noh, S. W. Hong, D. H. Kim, J. Y. Kim, H. H. Kim, D. J. Wong, W. S. Lee, "Charge Trapping Induced DRAM Data Retention Time Degradation under Wafer-Level Burn-in Stress," 2002 IEEE IRPS Proceedings, pp. 287-291.