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1
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84907680859
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The RF potential of high-performance 100nm CMOS technology
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V.C. Venezia, A. J. Scholten, C. Detcheverry, H. Boots, W. Jeamsaksiri, L.Grau, D.B.M. Klaassen, R.M.D.A Velghel, R. J. Havens, and L.F. Tiemeijer, "The RF potential of high-performance 100nm CMOS technology", ESSDERC 2002 conf. Proceedings, p. 491-494.
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ESSDERC 2002 Conf. Proceedings
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Venezia, V.C.1
Scholten, A.J.2
Detcheverry, C.3
Boots, H.4
Jeamsaksiri, W.5
Grau, L.6
Klaassen, D.B.M.7
Velghel, R.M.D.A.8
Havens, R.J.9
Tiemeijer, L.F.10
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3
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4544303654
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Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA
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accepted for publication, Honolulu, USA
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W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linien, S. Thijs, S. Jenei, C. Detcheverry,P. Wambacq, R. Velghe, S. Decoutere," Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA", accepted for publication 2004 symposium on VLSI circuits, Honolulu, USA.
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2004 Symposium on VLSI Circuits
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Jeamsaksiri, W.1
Mercha, A.2
Ramos, J.3
Linien, D.4
Thijs, S.5
Jenei, S.6
Detcheverry, C.7
Wambacq, P.8
Velghe, R.9
Decoutere, S.10
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4
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4544375267
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Low-power 5 GHz LNA and VCO in 90 nm RF CMOS
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accepted for publication, Honolulu, USA
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D. Linien, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R.Garcia, H. Jacobsson, P. Wambacq, S. Donnay and S. Decoutere," Low-power 5 GHz LNA and VCO in 90 nm RF CMOS", accepted for publication 2004 symposium on VLSI circuits, Honolulu, USA.
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2004 Symposium on VLSI Circuits
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Linien, D.1
Aspemyr, L.2
Jeamsaksiri, W.3
Ramos, J.4
Mercha, A.5
Jenei, S.6
Thijs, S.7
Garcia, R.8
Jacobsson, H.9
Wambacq, P.10
Donnay, S.11
Decoutere, S.12
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5
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84860924176
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www.semiconductors.philips.com/Philips_Models
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6
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77950830358
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Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain
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D. Linien, S. Thijs, W. Jeamsaksiri, M. I. Natarajan, V. De Heyn, V. Vassilev, G. Groeseneken, A.J. Schollen, G. Badenes, M. Jurczak, S. Decoutere, S. Donnay and P. Wambacq, "Design-driven Optimisation of a 90 nm RF CMOS Process by use of Elevated Source/Drain", ESSDERC 2003 conf. Proceedings, pp 43-46.
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ESSDERC 2003 Conf. Proceedings
, pp. 43-46
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Linien, D.1
Thijs, S.2
Jeamsaksiri, W.3
Natarajan, M.I.4
De Heyn, V.5
Vassilev, V.6
Groeseneken, G.7
Schollen, A.J.8
Badenes, G.9
Jurczak, M.10
Decoutere, S.11
Donnay, S.12
Wambacq, P.13
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7
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0031147079
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A 1.5-V 1.5-GHz CMOS: Low noise amplifier
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May
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D. K. Shaeffer and T. H. Lee, "A 1.5-V 1.5-GHz CMOS: Low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
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(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 745-759
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Shaeffer, D.K.1
Lee, T.H.2
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8
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0036160772
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Impact of intrinsic channel resistance on noise performance of CMOS LNA
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January
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J. Chen, and B. Shi, "Impact of Intrinsic Channel Resistance on Noise Performance of CMOS LNA", IEEE Electron Device Letters, vol. 23, No.1, January 2002, pp. 34-36.
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(2002)
IEEE Electron Device Letters
, vol.23
, Issue.1
, pp. 34-36
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Chen, J.1
Shi, B.2
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9
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22544433980
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Implementation of inductor based BSD protection for 5.5 GHz LNA in 90 nm RF CMOS - Concepts, constraint and solutions
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accepted for publication
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S. Thijs, M.I. Natarajan, D. Linien, T. Daenen, V. Vassilev, R. Degraeve, P. Wambacq, G. Groeseneken, "Implementation of Inductor Based BSD Protection for 5.5 GHz LNA in 90 nm RF CMOS - Concepts, Constraint and Solutions," accepted for publication EOS/ESD symposium 2004.
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EOS/ESD Symposium 2004
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Thijs, S.1
Natarajan, M.I.2
Linien, D.3
Daenen, T.4
Vassilev, V.5
Degraeve, R.6
Wambacq, P.7
Groeseneken, G.8
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10
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0035967020
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High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection
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March
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P. Leroux, and M. Steyaert, "High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection", Electronic Letters, vol. 37, no. 7, March 2001, pp. 467-469.
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(2001)
Electronic Letters
, vol.37
, Issue.7
, pp. 467-469
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Leroux, P.1
Steyaert, M.2
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11
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0036603909
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Significance of the failure criterion on transmission line pulse testing
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B. Keppens et al., "Significance of the failure criterion on transmission line pulse testing," Microel. Reliability 42, 2002, pp. 901-907.
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(2002)
Microel. Reliability
, vol.42
, pp. 901-907
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Keppens, B.1
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12
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0035509999
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A mixed signal design roadmap
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Nov.-Dec.
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R. Brederlow, W. Weber, J. Sauerer, S. Donnay, P. Wambacq, and M. Vertregt, "A mixed signal design roadmap", IEEE Design & Test of Computers, Vol. 18, No. 6, Nov.-Dec. 2001 pp. 34-46.
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(2001)
IEEE Design & Test of Computers
, vol.18
, Issue.6
, pp. 34-46
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Brederlow, R.1
Weber, W.2
Sauerer, J.3
Donnay, S.4
Wambacq, P.5
Vertregt, M.6
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13
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0141981869
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A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption
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H.W. Chiu, and S.S. Lu, "A 2.17 dB NF, 5 GHz Band Monolithic CMOS LNA with 10 mW DC Power Consumption", VLSI Circuits symposium 2002 conf. Proceedings, pp. 226-229.
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VLSI Circuits Symposium 2002 Conf. Proceedings
, pp. 226-229
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Chiu, H.W.1
Lu, S.S.2
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15
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12344270362
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A 5-6 GHz fully integrated CMOS LNA for a dual-band WLAN Receiver
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D. Mukherjee, J. Bhattacharjee, S. Chakaraborty, and Joy Laskar," A 5-6 GHz fully integrated CMOS LNA for a dual-band WLAN Receiver", RAWCON 2002 conf. Proceedings, pp. 213-215.
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RAWCON 2002 Conf. Proceedings
, pp. 213-215
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Mukherjee, D.1
Bhattacharjee, J.2
Chakaraborty, S.3
Laskar, J.4
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16
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0036287342
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Gain and frequency controllable sub-1V 5.8 GHz CMOS LNA
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May
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T. K. K. Tsang, and M. El-Gamal, "Gain and Frequency Controllable Sub-1V 5.8 GHz CMOS LNA.", ISCAS 2002 conf. Proceedings, Vol. 4.,pp.795-798, May 2002.
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(2002)
ISCAS 2002 Conf. Proceedings
, vol.4
, pp. 795-798
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Tsang, T.K.K.1
El-Gamal, M.2
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