Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 43-46

  Linten, D ^a,b   Thijs, S ^a   Jeamsaksiri, W ^a   Natarajan, M I ^a   De Heyn, V ^a   Vassilev, V ^c   Groeseneken, G ^c   Scholten, A J ^d   Badenes, G ^e   Jurczak, M ^a   Decoutere, S ^a   Donnay, S ^a   Wambacq, P ^b  

^a LMEC ^*  (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

^e ICFO INSTITUT DE CIENCIES FOTONIQUES   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELEVATED SOURCE/DRAIN; OPTIMISATIONS; RF-CMOS;

EID: 77950830358     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256806     Document Type: Conference Paper

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