SEU Mitigation for Half-Latches in Xilinx Virtex FPGAs

IEEE Transactions on Nuclear Science

Volumn 50, Issue 6 I, 2003, Pages 2139-2146

  Graham, Paul ^a   Caffrey, Michael ^a   Johnson, D Eric ^a,b   Rollins, Nathaniel ^b   Wirthlin, Michael ^b  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

^b BRIGHAM YOUNG UNIVERSITY   (United States)

Author keywords

Field programmable gate arrays (FPGAs); Half latches; Proton accelerator; Radiation effects; Single event upsets (SEUs)

Indexed keywords

COMPUTER SOFTWARE; DATA PROCESSING; ENCODING (SYMBOLS); FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; PARTICLE ACCELERATORS; POISSON RATIO; RADIATION EFFECTS; REDUNDANCY; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

HALF-LATCHES; PROTON FLUENCE; SINGLE-EVENT UPSETS (SEU);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 1242332766     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.820744     Document Type: Conference Paper

References (10)

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8. P. Graham, M. Caffrey, M Wirthlin, D. E. Johnson, and N. Rollins, "Reconfigurable computing in space: from current technology to reconfigurable systems-on-a-chip," in Proc. 2003 IEEE Aerospace Conf., Big Sky, MT, Mar. 2003, pp. T07_0603.1-T07_0603.12.
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