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Volumn 2003-January, Issue , 2003, Pages 92-97

SEU mitigation testing of Xilinx Virtex II FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HEAVY IONS; INTEGRATED CIRCUIT DESIGN; PROTON IRRADIATION; RADIATION HARDENING; RECONFIGURABLE HARDWARE; SPACE FLIGHT;

EID: 77649312126     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/REDW.2003.1281354     Document Type: Conference Paper
Times cited : (62)

References (7)
  • 1
  • 4
    • 34748900159 scopus 로고    scopus 로고
    • SEU Mitigation Techniques for Virtex FPGAs in Space Applications
    • C. Carmichael, E. Fuller, P. Blain, and M. Caffrey, "SEU Mitigation Techniques for Virtex FPGAs in Space Applications," MAPLD, 1999.
    • (1999) MAPLD
    • Carmichael, C.1    Fuller, E.2    Blain, P.3    Caffrey, M.4
  • 5
    • 66449107834 scopus 로고    scopus 로고
    • Single-Event Upset Susceptibility of the Xilinx Virtex II FPGA
    • C. Yui, G. Swift, and C. Carmichael, "Single-Event Upset Susceptibility of the Xilinx Virtex II FPGA," MAPLD, 2002.
    • (2002) MAPLD
    • Yui, C.1    Swift, G.2    Carmichael, C.3
  • 6
    • 11244320223 scopus 로고    scopus 로고
    • Correcting Single-Event Upsets Through Virtex Partial Configuration
    • June
    • C. Carmichael, "Correcting Single-Event Upsets Through Virtex Partial Configuration," Xilinx Application Note XAPP216, June, 2000.
    • (2000) Xilinx Application Note XAPP216
    • Carmichael, C.1
  • 7
    • 11044221639 scopus 로고    scopus 로고
    • Triple Module Redundancy Design Techniques for Virtex FPGAs
    • November
    • C. Carmichael, "Triple Module Redundancy Design Techniques for Virtex FPGAs," Xilinx Application Note XAPP197, November, 2001.
    • (2001) Xilinx Application Note XAPP197
    • Carmichael, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.