A current shaping methodology for lowering em disturbances in asynchronous circuits

Microelectronics Journal

Volumn 35, Issue 6 SPEC ISS., 2004, Pages 531-540

  Panyasak, Dhanistha ^a,b   Sicard, Gilles ^a   Renaudin, Marc ^a  

^a TIMA LABORATORY   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Architectural description; Asynchronous digital circuit; Electromagnetic emission reduction; Force directed scheduling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DATA PROCESSING; EMBEDDED SYSTEMS; NETWORK PROTOCOLS; NETWORKS (CIRCUITS); SIGNAL INTERFERENCE;

ARCHITECTURAL DESCRIPTION; ASYNCHRONOUS DIGITAL CIRCUITS; ELECTROMAGNETIC EMISSION REDUCTION; FORCE DIRECTED SCHEDULING;

ELECTROMAGNETIC WAVES;

EID: 1942439144     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2003.11.005     Document Type: Article

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