Clock Skew Optimization for Peak Current Reduction

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 117-130

  Benini, L ^a,c,d   Vuillod, P ^a,b,e   Bogliolo, A ^a,c   De Micheli, G ^a,d,f,g  

^a STANFORD UNIVERSITY   (United States)

^b GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d IEEE   (United States)

^e INP Grenoble ENSIMAG   (France)

^f Stanford University   (United States)

^g NATO Adv Stud Institutes H   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC CURRENT CONTROL; ELECTRIC LOSSES; FLIP FLOP CIRCUITS; OPTIMIZATION; TIMING CIRCUITS;

BENCHMARK CIRCUITS; CLOCK SKEW; CURRENT PEAKS;

DIGITAL CIRCUITS;

EID: 0031170516     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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