A surface-potential-based high-voltage compact LDMOS transistor model

IEEE Transactions on Electron Devices

Volumn 52, Issue 5, 2005, Pages 999-1007

  Aarts, Annemarie ^a   D'Halleweyn, Nele ^b   van Langevelde, Ronald ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b Arnold and Siedsma   (Belgium)

Author keywords

High voltage MOS; Integrated circuit design; LDMOS; Modeling; Silicon on insulator (SOI)

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; POWER INTEGRATED CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; SURFACE PROPERTIES; THERMAL EFFECTS; THRESHOLD VOLTAGE;

COMPACT TRANSISTOR MODEL; DRIFT REGION; HIGH VOLTAGE MOS; SURFACE POTENTIAL; TIME DEPENDENT BEHAVIOR;

SEMICONDUCTOR DEVICE MODELS;

EID: 18844462474     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.846335     Document Type: Article

References (22)

1. J. A. van der Pol et al., "A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications," in Proc. ISPSD, 2000, pp. 327-330.
2. R. S. Scott, G. A. Franz, and J. L. Johnson, "An accurate model for power DMOSFETs including interelectrode capacitances," IEEE Trans. Power Electron., vol. 6, no. 2, pp. 192-198, Mar. 1991.
3. J. Jang, T. Arnborg, Z. Yu, and R. W. Dutton, "Circuit model for power LDMOS including quasi-saturation," in Proc. SISPAD, 1999, pp. 15-18.
4. N. Hefyene, E. Vestiel, B. Bakeroot, C. Anghel, S. Frere, A. M. Ionescu, and R. Gillon, "Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET," in Proc. SISPAD, 2002, pp. 203-206.
5. A. C. T. Aarts, M. J. Swanenberg, and W. J. Kloosterman, "Modeling of high-voltage SOI-LDMOS transistors including self-heating," in Proc. SISPAD, 2001, pp. 246-249.
6. J. Victory, C. C. Mc Andrew, R. Thoma, K. Joardar, M. Kniffin, S. Merchant, and D. Moncoqut, "A physically-based compact model for LDMOS transistors," in Proc. SISPAD, 1998, pp. 271-274.
7. Y. Kim, J. G. Fossum, and R. K. Williams, "New physical insights and models for high-voltage LDMOST IC CAD," IEEE Trans. Electron Devices, vol. 38, no. 7, pp. 1641-1649, Jul. 1991.
8. Y. Chung and D. E. Burk, "A physically based DMOS transistor model implemented in SPICE for advanced power ID TCAD," in Proc. ISPSD, 1995, pp. 340-345.
9. M. Y. Hong and D. A. Antoniadis, Theoretical analysis and modeling of submicron channel length DMOS transistors," IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1614-1622, Sep. 1995.
10. Y. Chung, "LADISPICE-1.2: A nonplanar-drift lateral DMOS transistor model and its application to power IC TCAD," Inst. Elect. Eng., Proc. Circuits Devices Syst., vol. 147, no. 4, pp. 219-227, 2000.
11. C. M. Liu, F. C. Shone, and J. B. Kuo, "A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation," in Proc. ISPSD, 1995, pp. 321-324.
12. Y. Subramanian, P. O. Lauritzen, and K. R. Green, "A compact model for an IC lateral diffused MOSFET using lumped-charge methodology," in Proc. Modeling Simulation Microsystems, 1999, pp. 284-288.
13. N. D'Halleweyn, J. Benson, M. Swanenberg, and W. Redman-White, "A compact model for silicon-on-insulator LDMOST, including accumulation, lateral doping gradient and high-side behavior," in Proc. Silicon-on-Insulator Technology Devices, 2001, pp. 187-192.
14. N. D'Halleweyn, L. Tiemeijer, J. Benson, M. Swanenberg, and W. Redman-White, "Charge model for SOI-LDMOST with lateral doping gradient," in Proc. ISPSD, 2001, pp. 291-294.
15. A. C. T. Aarts and R. van Langevelde, "A robust and physically based compact SOI-LDMOS model," in Proc. ESSDERC, 2002, pp. 455-458.
16. C. C. McAndrew and J. J. Victory, "Accuracy of approximations in MOSFET charge models," IEEE Trans. Electron Devices, vol. 49, no. 1. pp. 72-81, Jan. 2002.
17. R. van Langevelde and F. M. Klaassen, "An explicit surface-potential-based MOSFET model for circuit simulation," Solid State Electron., vol. 44, pp. 409-418, 2000.
18. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999.
19. K. Joardar, K. K. Gullapulli, C. C. McAndrew, M. E. Burnham, and A. Wild, "An improved MOSFET model for circuit simulation," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 134-148, Jan. 1998.
20. S.-Y. Oh, D. E. Ward, and R. W. Dutton, "Transient analysis of MOS transistors," J. Solid-State Circuits, vol. SSC-15, pp. 636-643, 1980.
21. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, "MOS Model 11, Level 1101," Philips Electronics N.V., Unclassified Report NL-UR 2002/802, 2002.
22. Compact transistor models. Philips Semiconductors. [Online] Available: www.semiconductors.philips.com/Philips_Models