LADISPICE-1.2: A nonplanar-drift lateral DMOS transistor model and its application to power 1C TCAD

IEE Proceedings: Circuits, Devices and Systems

Volumn 147, Issue 4, 2000, Pages 219-227

  Chung, Y ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; COMPUTER SOFTWARE; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS;

SOFTWARE PACKAGE LADISPICE-1.2;

MOSFET DEVICES;

EID: 0034249854     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20000411     Document Type: Article

References (16)

1. CLAESSEN, H.R., and VAN DER ZEE, P.: 'An accurate de model for hiah-voltace lateral DMOS transistors suited for CACD' IEEE Trails"Electron Devices, 19S6, ED-33, pp. 1964-1970
2. KIM, Y.-S., and POSSUM, J.G.: 'Physical DMOST modelling for high-voltaee 1C CAD' IEEE Trans. Electron Devices, 1990, 37, pp. 797-803
3. KIM, Y.-S., POSSUM, J.G., and WILLIAMS, R.K.: 'New physical insights and models for hish-voltaee LDMOST 1C CAD' IEEE Trans. Electron Devices, 199C38, pp.~I641-1649
4. PAREDES,:., HIDALGO, S., BERTA, P., FERNANDEZ, J., REBOLLO, J., and MILLAN, J.: 'A steady-state VDMOS transistor model' IEEE Trans. Electron Devices, 1992, 39, pp. 712-719
5. LIU, C.-M., LÇU, K.-H., and KUO, J.B.: '77 K versus 300 K operation: The quasi-saturation behavior of a DMOS device and its fully analytical model' IEEE Trans. Electron Devices, 1993, 40, pp. 16361644
6. BUDIHARDJO, I., and LAUR1TZEN, P.O.: "The lumped-charge power MOSFET model, including parameter extraction' IEEE Tram. Power Electron., 1995, 10, pp. 379-387
7. HONG, M.Y., and ANTONIADIS, D.A.: 'Theoretical analysis and modelling of submicron channel length DMOS transistors' IEEE Trans. Electron Devices, 1995,42, pp. 1614-1622
8. VICTORY, J.J., SANCHEZ.J.J., DEMASSA, T.A., and WELFERT, B.D.: 'A static, physical VDMOS model based on the charge-sheet model' IEEE Trans. Electron Devices, 1996, 43, pp. 157-164
9. CHUNG, Y.: 'Semi-numerical static model for nonplanar-drift lateral DMOS transistor' IEE Proc., Circuits Devices Syst., 1999, 146, pp. 139-147
10. GUMMEL, H.K., and POON, H.C.: 'An integral charge control model of bipolar transistors' Bell Syst. Tech. J., 1970,49, pp. 827-852
11. POSSUM, J.G., and SHIBIB, M.A.: 'An analytic model for minoritycarrier transport in heavily doped regions of silicon devices' IEEE Trans. Electron Devices, 1981, EB-28, pp. 1018-1025
12. MCDONALD, R.J., and POSSUM, J.G.: 'High-voltage device modelling for SPICE simulation of HVICs' IEEE Trans. Compiit.-Aided Des. Intcgr. Circuits Syst., 1988,7, pp. 425-432
13. OH, S.-Y., WARD, D.E., and DUTTON, R.W.: Transient analysis of MOS transistors' IEEE J. Solid-Slate Circuits, 1980, SC-15, pp. 636-643
14. NAGEL, L.W.: 'SPICE2: A computer program to simulate semiconductor circuits'. Memo. ERL-M520, Electronics Research Lab., University of California, Berkeley, 1975
15. SHEN, Z., and CHOW, T.P.: 'Modeling and characterisation of the insulated gate bipolar transistor (IGBT) for SPICE simulation'. -Proceedings of the 5th international symposium on Power semiconductor devices and ICs, Monterey, California, USA, May 1993, pp. 165-170
16. HEFNER, A.R.: 'An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT)' IEEE Trans. Power Electron., 1990, 5, pp. 459-468