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Volumn , Issue , 2002, Pages 455-458

A robust and physically based compact SOI-LDMOS model

Author keywords

[No Author keywords available]

Indexed keywords

BIAS CONDITIONS; COMPUTATION TIME; DOPING GRADIENTS; DRIFT REGIONS; IMPROVED CONVERGENCE; OPERATING TEMPERATURE; PHYSICALLY BASED; TERMINAL VOLTAGES;

EID: 47749125258     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194966     Document Type: Conference Paper
Times cited : (5)

References (11)
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    • J.A. van der Pol et al., "A-BCD: An Economic 100V RESURF Silicon-On-Insulator BCD Technology for Consumer and Automotive Applications", Proc. ISPSD, 2000, pp. 327-330.
    • (2000) Proc. ISPSD , pp. 327-330
    • Pol Der Van, J.A.1
  • 2
    • 0029192597 scopus 로고
    • A closed-form physical back-gate-bias dependent quasi-saturation model for SOI Lateral DMOS devices with self-heating for circuit simulation
    • C.M. Liu et al., "A Closed-form Physical Back-Gate-Bias Dependent Quasi-saturation Model for SOI Lateral DMOS Devices with Self-Heating for Circuit Simulation", Proc. ISPSD, 1995, pp. 321-324.
    • (1995) Proc. ISPSD , pp. 321-324
    • Liu, C.M.1
  • 3
    • 18844388820 scopus 로고    scopus 로고
    • Modelling of high-voltage SOI-LDMOS transistors including self-heating
    • A.C.T. Aarts et al., "Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating", Proc. SISPAD, 2001,pp. 246-249.
    • (2001) Proc. SISPAD , pp. 246-249
    • Aarts, A.C.T.1
  • 4
    • 0033284542 scopus 로고    scopus 로고
    • Circuit model for power LDMOS including quasi-saturation
    • J. Jang et al., "Circuit Model for Power LDMOS including Quasi-Saturation", Proc. SISPAD, 1999, pp. 15-18.
    • (1999) Proc. SISPAD , pp. 15-18
    • Jang, J.1
  • 5
    • 0002546460 scopus 로고    scopus 로고
    • A physically-based compact model for LDMOS transistors
    • J. Victory et al., "A Physically-Based Compact Model for LDMOS Transistors ", Proc. SISPAD, 1998, pp. 271-274.
    • (1998) Proc. SISPAD , pp. 271-274
    • Victory, J.1
  • 6
    • 0029379418 scopus 로고
    • Theoretical analysis and modeling of submicron channel length DMOS transistors
    • M.Y. Hong and D.A. Antoniadis, "Theoretical Analysis and Modeling of Submicron Channel Length DMOS Transistors", IEEE Trans. Electron Devices, Vol. 42, No 9, 1995,pp. 1614-1622.
    • (1995) IEEE Trans. Electron Devices , vol.42 , Issue.9 , pp. 1614-1622
    • Hong, M.Y.1    Antoniadis, D.A.2
  • 7
    • 0034249854 scopus 로고    scopus 로고
    • LADiSPICE-1.2: A nonplanar-drift lateral DMOS transistor model and its application to power IC TCAD
    • Y. Chung, "LADiSPICE-1.2: A Nonplanar-Drift Lateral DMOS Transistor Model and its Application to Power IC TCAD", IEE Proc.-Circuits Devices Syst., Vol. 147, No 4, 2000,pp.219-227.
    • (2000) IEE Proc.-Circuits Devices Syst. , vol.147 , Issue.4 , pp. 219-227
    • Chung, Y.1
  • 8
    • 0026189298 scopus 로고
    • New physical insights and models for high-voltage LDMOST IC CAD
    • Y. Kim et al., "New Physical Insights and Models for High-Voltage LDMOST IC CAD", IEEE Trans. Electron Devices, Vol. 38, No 7, 1991, pp. 1641-1649.
    • (1991) IEEE Trans. Electron Devices , vol.38 , Issue.7 , pp. 1641-1649
    • Kim, Y.1
  • 10
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    • An explicit surface-potential-based MOSFET model for circuit simulation
    • R. van Langevelde and F.M. Klaassen, "An Explicit Surface-potential-based MOSFET Model for Circuit Simulation", Solid-State Electronics, Vol. 44, 2000, pp. 409 - 418. See also http://www.semiconductors.philips.com/Philips-Models.
    • (2000) Solid-State Electronics , vol.44 , pp. 409-418
    • Van Langevelde, R.1    Klaassen, F.M.2
  • 11
    • 0031646543 scopus 로고    scopus 로고
    • An improved MOSFET model for circuit simulation
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.