Charge model for SOI LDMOST with lateral doping gradient

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2001, Pages 291-294

  D'Halleweyn, N V ^a   Tiemeijer, L F ^a   Benson, J ^a   Redman White, W ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; MATHEMATICAL MODELS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

LATERAL DOPING GRADIENTS;

MOS DEVICES;

EID: 0034836005     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation
2. A physically-based compact model for LDMOS transistors
3. A compact model for SOI LDMOST, including accumulation, lateral doping gradient and high-side behaviour
4. An accurate DC model for high-voltage lateral DMOS transistors suited for CACD
5. An accurate model for power DMOSFETs including interelectrode capacitances
6. Application of the MOS charge-sheet model to nonuniform doping along the channel
7. Transient analysis of MOS transistors
8. Physical DMOST modelling for HV ICCAD
9. A physically based compact model of partially depleted SOI MOSFETs for analogue circuit simulation