-
1
-
-
0024170325
-
"Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness"
-
K. Naruke, S. Taguchi, and M. Wada, "Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness," in IEDM Tech. Dig., 1988, p. 424.
-
(1988)
IEDM Tech. Dig.
, pp. 424
-
-
Naruke, K.1
Taguchi, S.2
Wada, M.3
-
2
-
-
0031634344
-
"A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories"
-
Y. Takeuchi et al., "A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories," in VLSI Symp. Dig. Tech., 1998, pp. 102-103.
-
(1998)
VLSI Symp. Dig. Tech.
, pp. 102-103
-
-
Takeuchi, Y.1
-
3
-
-
0141761545
-
"A novel self-align shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs"
-
M. Ichige et al., "A novel self-align shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs," in VLSI Symp. Dig. Tech., 2003, pp. 89-90.
-
(2003)
VLSI Symp. Dig. Tech.
, pp. 89-90
-
-
Ichige, M.1
-
4
-
-
0000090297
-
"Layered tunnel barriers for nonvolatile memory devices"
-
K. K. Likharev, "Layered tunnel barriers for nonvolatile memory devices," Appl. Phys. Lett., vol. 73, p. 2137, 1998.
-
(1998)
Appl. Phys. Lett.
, vol.73
, pp. 2137
-
-
Likharev, K.K.1
-
5
-
-
0036639637
-
"Material issues for layered tunnel barrier structures"
-
J. Casperson et al., "Material issues for layered tunnel barrier structures," J. Appl. Phys., vol. 92, p. 261, 2002.
-
(2002)
J. Appl. Phys.
, vol.92
, pp. 261
-
-
Casperson, J.1
-
6
-
-
0038732556
-
"VARIOT: A novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices"
-
Jan
-
B. Govoreanu et al., "VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices," IEEE Trans. Electron Devices, vol. 50, no. 1, p. 99, Jan. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.1
, pp. 99
-
-
Govoreanu, B.1
-
7
-
-
0022298385
-
"The effect of write/erase cycling on data loss in EEPROMs"
-
D. A. Baglee and M. C. Smayling, "The effect of write/erase cycling on data loss in EEPROMs," in IEDM Tech. Dig., 1985, p. 624.
-
(1985)
IEDM Tech. Dig.
, pp. 624
-
-
Baglee, D.A.1
Smayling, M.C.2
-
8
-
-
0024125531
-
2 films"
-
Dec
-
2 films," IEEE Trans. Electron Devices, vol. ED-35, no. 12, p. 2259, Dec. 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.ED-35
, Issue.12
, pp. 2259
-
-
Olivo, P.1
Nguyen, T.N.2
Ricco, B.3
-
9
-
-
0026254804
-
"Stress-Induced oxide leakage"
-
Aug
-
R. Rofan and C. Hu, "Stress-induced oxide leakage," IEEE Electron Devices Lett., vol. 12, no. 8, p. 632, Aug. 1991.
-
(1991)
IEEE Electron Devices Lett.
, vol.12
, Issue.8
, pp. 632
-
-
Rofan, R.1
Hu, C.2
-
11
-
-
0009682265
-
"Unified analytic model of direct and Fowler-Nordheim tunnel currents through ultrathin gate oxides"
-
J. H. Khairurrijal et al., "Unified analytic model of direct and Fowler-Nordheim tunnel currents through ultrathin gate oxides," Appl. Phys. Lett., vol. 77, p. 3580, 2000.
-
(2000)
Appl. Phys. Lett.
, vol.77
, pp. 3580
-
-
Khairurrijal, J.H.1
-
12
-
-
0037349764
-
"Enhancement of the effective tunnel mass in ultrathin silicon dioxide layers"
-
M. Städele et al., "Enhancement of the effective tunnel mass in ultrathin silicon dioxide layers," J. Appl. Phys., vol. 93, p. 2681, 2003.
-
(2003)
J. Appl. Phys.
, vol.93
, pp. 2681
-
-
Städele, M.1
-
13
-
-
0029701167
-
"Limitations on oxide thickness in Flash EEPROM applications"
-
E. F. Runnion et al., "Limitations on oxide thickness in Flash EEPROM applications," in Proc. IRPS, 1996, p. 93.
-
(1996)
Proc. IRPS
, pp. 93
-
-
Runnion, E.F.1
-
14
-
-
0043028448
-
"Scaling effects on gate leakage current"
-
Dec
-
H. Watanabe, K. Matsuzawa, and S. Takagi, "Scaling effects on gate leakage current," IEEE Trans. Electron Devices, vol. 50, no. 12, p. 1779, Dec. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.12
, pp. 1779
-
-
Watanabe, H.1
Matsuzawa, K.2
Takagi, S.3
-
15
-
-
18844430683
-
"Determination of tunnel mass and thickness of gate oxide including poly-Si/SiO2 and Si/SiO2 interfacial transition layers"
-
H. Watanabe, D. Matsushita, and K. Muraoka, "Determination of tunnel mass and thickness of gate oxide including poly-Si/SiO2 and Si/SiO2 interfacial transition layers," in Proc. SSDM, 2004.
-
(2004)
Proc. SSDM
-
-
Watanabe, H.1
Matsushita, D.2
Muraoka, K.3
-
17
-
-
0019081768
-
"Dopant segregation in polycrystalline silicon"
-
M. M. Mandurah, "Dopant segregation in polycrystalline silicon," J. Appl. Phys., vol. 51, p. 5755, 1980.
-
(1980)
J. Appl. Phys.
, vol.51
, pp. 5755
-
-
Mandurah, M.M.1
|