A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 419-425

  Choi, Jong Sang ^a   Hwang, Moon Sang ^a   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

Author keywords

Adaptation; Adaptive equalizer; Cable equalizer; CMOS; Common mode feedback (CMFB); Enhanced low frequency gain control; Equalizer; Gain control; Merged path

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITORS; CMOS INTEGRATED CIRCUITS; COAXIAL CABLES; COMPARATOR CIRCUITS; COMPUTER SIMULATION; GAIN CONTROL; HIGH PASS FILTERS; INTEGRATED CIRCUIT LAYOUT; LOW PASS FILTERS; NATURAL FREQUENCIES; SOLID STATE RECTIFIERS;

ADAPTIVE EQUALIZER; CABLE EQUALIZER; COMMON MODE FEEDBACK; ENHANCED LOW FREQUENCY GAIN CONTROL;

EQUALIZERS;

EID: 1542396068     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.822774     Document Type: Article

References (16)

1. D. A. Johns, and D. Essig, "Integrated circuits for data transmission over twisted-pair channels," IEEE J. Solid-State Circuits, vol. 32, pp. 298-406, Mar. 1997.
2. A. Fiedler et al., "A 1.0625 Gb/s transceiver with 2 x-oversampling and transmit signal pre-emphasis," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp. 238-239.
3. W. J. Dally and J. Poulton, "Transmitter equalization for 4-Gb/s signaling," IEEE Micro, vol. 17, pp. 48-56, Jan./Feb. 1997.
4. R. Farjad-Rad, C.K. Yang, M. Horowitz, and T. H. Lee, "A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter," IEEE J. Solid-State Circuits, vol. 34, pp. 580-585, May 1999.
5. J. Sonntag et al., "An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS," in Proc. IEEE Custom Integrated Circuits Conf., 2002, pp. 363-366.
6. K. Gotoh et al., "A 2B parallel 1.25-Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1999, pp. 180-181.
7. R. Farjad-Rad, C.K. Yang, M. Horowitz, and T. H. Lee, "A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE J. Solid-State Circuits, vol. 35, pp. 757-764, May 2000.
8. J. Sim et al., "840-Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-Processor communication," in Symp. VLSI Circuits Dig. Tech. Papers, June 1999, pp. 23-24.
9. Y. Kudoh, M. Fukaishi, and M. Mizuno, "A 0.13-μm CMOS 5-Gb/s 10-meter 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer," IEEE J. Solid-State Circuits, vol. 38, pp. 741-746, May 2003.
10. A. J. Baker, "An adaptive cable equalizer for serial digital video rates to 400 Mb/s," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 174-175.
11. M. H. Shakiba, "A 2.5 Gb/s adaptive cable equalizer," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1999, pp. 396-397.
12. J. N. Babanezhad, "A 3.3-V analog adaptive line-equalizer for fast ethernet data connection," in Proc. IEEE Custom Integrated Circuit Conf., May 1998, pp. 343-346.
13. G. P. Hartman, K. W. Martin, and A. McLaren, "Continuous-time adaptive-analog coaxial cable equalizer in 0.5 μm CMOS," in Proc. Int. Symp. Circuits and Systems, 1999, pp. 97-100.
14. J.-S. Choi, M.-S. Hwang, and D.-K. Jeong, "A CMOS 3.5 Gb/s continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting," in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 103-106.
15. O. E. Akcasu, "High capacitance structures in a semiconductor device," U.S. Patent 5,208,725, May 4, 1993.
16. Z. Wang, "Full-wave precision rectification that is performed in current domain and very suitable for CMOS implementation," IEEE Trans. Circuits Syst. I, vol. 39, pp. 456-462, June 1992.