Schedule-aware performance estimation of communication architecture for efficient design space exploration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 5, 2005, Pages 539-552

  Kim, Sungchan ^a   Im, Chaeseok ^a   Ha, Soonhoi ^b  

^a Seoul National University   (South Korea)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Communication architecture; Design space exploration; Performance estimation; Queueing theory

Indexed keywords

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ERRORS; ESTIMATION; MATHEMATICAL MODELS; PERFORMANCE; POLYNOMIALS; QUEUEING THEORY; SCHEDULING; TELECOMMUNICATION NETWORKS; TOPOLOGY;

COMMUNICATION ARCHITECTURE; DESIGN SPACE EXPLORATION; PERFORMANCE ESTIMATION; SYSTEM-ON-A-CHIP (SOC);

INTEGRATED CIRCUIT LAYOUT;

EID: 18744389177     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842912     Document Type: Article

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