Layout conscious bus architecture synthesis for deep submicron systems on chip

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 108-113

  Thepayasuwan, Nattawut ^a   Doboli, Alex ^a  

^a Stony Brook University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS ARCHITECTURE (BA) SYNTHESIS; DEEP SUBMICRON SYSTEMS; SYSTEMS ON CHIP (SOC); VERY DEEP SUBMICRON (VSDM) DESIGNS; BUS ARCHITECTURE; BUS ARCHITECTURE SYNTHESIS; COMMUNICATION DELAYS; NETWORK PROCESSOR; SYNTHESIS ALGORITHMS; SYSTEM LEVEL DESIGN; SYSTEMS ON CHIPS; VERY DEEP SUB MICRONS;

ALGORITHMS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PERSONAL COMPUTERS; SCHEDULING; SIMULATED ANNEALING; SPURIOUS SIGNAL NOISE; EXHIBITIONS; MICROPROCESSOR CHIPS;

MICROPROCESSOR CHIPS; DESIGN;

EID: 3042515561     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268835     Document Type: Conference Paper

References (13)

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