Analysis and Measurement of Fault Coverage in a Combined ATE and BIST Environment

IEEE Transactions on Instrumentation and Measurement

Volumn 53, Issue 2, 2004, Pages 300-307

  Hashempour, Hamidreza ^a   Meyer, Fred Jackie ^a   Lombardi, Fabrizio ^a  

^a Northeastern University   (United States)

Author keywords

Automatic test equipment (ATE); Built in self test (BIST); Fault coverage; Hybrid BIST

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; FUNCTIONS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); RANDOM PROCESSES; VECTORS;

AUTOMATIC TEST EQUIPMENT (ATE); BUILT-IN SELF-TEST (BIST); FAULT COVERAGE; HYBRID BIST;

ELECTRIC FAULT CURRENTS;

EID: 1842534194     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2003.822710     Document Type: Article

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