Exploiting operation level parallelism through dynamically reconfigurable datapaths

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 337-342

  Huang, Zhining ^a   Malik, Sharad ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MOTION PICTURES; VERY LONG INSTRUCTION WORD ARCHITECTURE;

NON-RECURRING ENGINEERING (NRE);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0036059443     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513918.514006     Document Type: Conference Paper

References (17)

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7. Managing dynamic reconfiguration overhead in system-on-a-chip design using reconfigurable datapaths and optimized interconnection networks
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9. Product overview: Intel® Pentium® 4 processor-based workstations
10. System level design: Orthogonolization of concerns and platform-based design
11. Instruction-level parallelism for reconfigurable computing