Shmoo plotting: The black art of IC testing

IEEE Design and Test of Computers

Volumn 14, Issue 3, 1997, Pages 90-97

  Baker, Keith ^a,b,c,d,e   Van Beers, Jos ^b,f  

^a Philips ED and T   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c UNIVERSITY OF ESSEX   (United Kingdom)

^d IEEE   (Netherlands)

^e IEEE ^*  (Netherlands)

^f Hogeschool Eindhoven   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; QUALITY ASSURANCE; VALUE ENGINEERING;

SHMOO PLOTTING;

INTEGRATED CIRCUIT TESTING;

EID: 0031190581     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.606005     Document Type: Article

References (4)

1. R.E. Huston, "Testing Semiconductor Memories," Proc. Int'l Test Conf., IEEE Computer Society, Los Alamitos, Calif., 1973, pp. 27-82.
2. R.E. Huston, ITC Tutorial Notes, IEEE Computer Society, Los Alamitos, Calif., 1996.
3. S.P. Allan, "Low-Cost Workstation with Enhanced Performance and I/O Capabilities," Hewlett-Packard J., June 1997, pp. 82-88.
4. W. Maly, A.J. Strojwas, and S.W. Director, "VLSI Yield Prediction and Estimation: A Unified Framework," IEEE Trans. Computer-Aided Design, Vol. CAD-5, No. 1, Jan. 1986, pp. 114-130.