Power supply ramping for quasi-static testing of PLLs

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 980-987

  De Gyvez, José Pineda ^a   Gronthoud, Guido ^a   Cenci, Cristiano ^a   Posch, Martin ^b   Burger, Thomas ^b   Koller, Manfred ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT TESTING; JITTER; MATHEMATICAL MODELS; POWER SUPPLY CIRCUITS; THROUGHPUT; TRANSISTORS;

DEFECT-ORIENTED TESTING (DOT); FAULT COVERAGE; QUASI-STATIC TESTING; WAFER TESTING;

PHASE LOCKED LOOPS;

EID: 18144375978     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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