DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 210-213

  Goteti, Prashant ^a   Devarayanadurg, Giri ^a   Soma, Mani ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; STANDARDS; VARIABLE FREQUENCY OSCILLATORS;

CHARGE PUMP PHASE LOCKED LOOPS (CP PLL); DESIGN FOR TEST (DFT) TECHNIQUE;

INTEGRATED CIRCUIT TESTING;

EID: 0030649391     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)