An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2004, Pages 227-230

  Krishnamohan, Srivathsan ^a   Mahapatra, Nihar R ^a  

^a Michigan State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC POTENTIAL; ERROR ANALYSIS; ERROR DETECTION; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; ONLINE SYSTEMS; ROBUSTNESS (CONTROL SYSTEMS);

ERROR MASKING; SOFT ERRORS; TRIPLE MODULAR REDUNDANCY (TMR); VOLTAGE FLUCTUATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 14844334935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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