VLSI architecture for discrete wavelet transform based on B-spline factorization

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 346-350

  Huang, Chao Tsung ^a   Tseng, Po Chih ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Art; Channel bank filters; Chaos; Convolution; Digital signal processing; Discrete wavelet transforms; Filter bank; Finite impulse response filter; Spline; Very large scale integration

Indexed keywords

CHAOS THEORY; CONVOLUTION; DIGITAL SIGNAL PROCESSING; FACTORIZATION; FILTER BANKS; FIR FILTERS; IMPULSE RESPONSE; INTEGRATED CIRCUIT TESTING; INTERPOLATION; SIGNAL PROCESSING; SPLINES; VLSI CIRCUITS; WAVELET TRANSFORMS;

ART; B-SPLINE FACTORIZATION; CHANNEL BANK FILTERS; CRITICAL PATHS; POLY-PHASE DECOMPOSITIONS; PROPOSED ARCHITECTURES; SMALL AREA; VLSI ARCHITECTURES;

DISCRETE WAVELET TRANSFORMS;

EID: 84943278286     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235694     Document Type: Conference Paper

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