A 2-5GHz low jitter 0.13μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 147-150

  Maxim, Adrian ^a  

^a Integrated Products   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT MATCHING; FREQUENCY RANGE; SUNMICRON; WIDEBAND;

CMOS INTEGRATED CIRCUITS; DETECTORS; FREQUENCIES; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE; TRANSISTORS;

JITTER;

EID: 17044434579     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. I. Yang, J. Greason, K. Wong, "A PLL clock generator with 5 to 110MHz of lock range for microprocessors", IEEE JSSC, vol. 27, no.11, pp. 1599-1607, Nov. '92.
2. J. Maneatis, "Low jitter process independent DLL and PLL based on self-biased techniques", IEEE JSSC, vol. 31, no. 11, pp. 1723-1732.
3. K. Shu, "A 2.4GHz monolithic fractional-N frequency synthesizer with loop capacitance multiplier", IEEE JSSC, vol.38,no.6,pp.866-874..
4. D. Mijuskovic, et al, "Cell based fully integrated CMOS frequency synthesizer", IEEE JSSC, vol. 29, no. 3, pp. 271-279, March '94.
5. A. Maxim, et al, "A low jitter 125-1250MHz process independent 0.18μm CMOS PLL based on a sample-reset loop filter", IEEE JSSC, vol.36, no. 11, pp.1673-1683, Nov. '01.
6. J. Lee, B. Kim, "A low noise fast lock phase locked loop wit adaptive bandwidth control", IEEE JSSC, vol.35, no.8, pp.1137-1145, Aug. '00
7. A. Maxim, "A 160-2550MHz CMOS Active Clock Deskewing PLL Using Analog Phase Interpolation", IEEE ISSCC 2004, pp.346-347.