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Volumn 147, Issue 6, 2000, Pages 375-382
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Two systolic architectures for multiplication in GF(2m)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COMPUTER HARDWARE;
DATA COMMUNICATION SYSTEMS;
DIGITAL ARITHMETIC;
FLIP FLOP CIRCUITS;
RANDOM NUMBER GENERATION;
FINITE FIELDS;
SYSTOLIC ARCHITECTURES;
SYSTOLIC ARRAYS;
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EID: 0034313273
PISSN: 13502387
EISSN: None
Source Type: Journal
DOI: 10.1049/ip-cdt:20000785 Document Type: Article |
Times cited : (23)
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References (15)
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