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Volumn 147, Issue 6, 2000, Pages 375-382

Two systolic architectures for multiplication in GF(2m)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA COMMUNICATION SYSTEMS; DIGITAL ARITHMETIC; FLIP FLOP CIRCUITS; RANDOM NUMBER GENERATION;

EID: 0034313273     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20000785     Document Type: Article
Times cited : (23)

References (15)
  • 3
    • 0024105183 scopus 로고
    • Algorithms for multiplication in Galois field for implementation using systolic arrays
    • BANDYOPADHYAY, S., and SENGUPTA, A.: Algorithms for multiplication in Galois field for implementation using systolic arrays, IEE Proc. E, Comput. Digit. Tech., 1988, 135, (6), pp. 336-340
    • (1988) IEE Proc. E, Comput. Digit. Tech. , vol.135 , Issue.6 , pp. 336-340
    • Bandyopadhyay, S.1    Sengupta, A.2
  • 5
    • 0032023744 scopus 로고    scopus 로고
    • Efficient semisystolic architectures for finite-field arithmetic
    • JAIN, S.K., SONG, L., and PARHI, K.K.: Efficient semisystolic architectures for finite-field arithmetic, IEEE Trans. VLSI Syst., 1998, 6, (1), pp. 101-113
    • (1998) IEEE Trans. VLSI Syst. , vol.6 , Issue.1 , pp. 101-113
    • Jain, S.K.1    Song, L.2    Parhi, K.K.3
  • 11
    • 0024771510 scopus 로고
    • Systolic architecture for finite field exponentiation
    • GHAFOOR, A., and SINGH, A.: Systolic architecture for finite field exponentiation, IEE Proc., Comput. Digit. Tech., 1989, 136, (6) pp. 465-470
    • (1989) IEE Proc., Comput. Digit. Tech. , vol.136 , Issue.6 , pp. 465-470
    • Ghafoor, A.1    Singh, A.2
  • 14
    • 0021455219 scopus 로고
    • On supercomputing with systolic/wavefront array processors
    • KUNG, S.Y.: On supercomputing with systolic/wavefront array processors, Proc. IEEE, 1984, pp. 867-884
    • (1984) Proc. IEEE , pp. 867-884
    • Kung, S.Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.