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Volumn 15, Issue 3, 1997, Pages 233-245

Novel Radix Finite Field Multiplier for GF(2m)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC;

EID: 0031100680     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (14)

References (19)
  • 1
    • 0026186630 scopus 로고
    • Systolic array implementation of multipliers for finite fields
    • July
    • C.L. Wang and J.L. Lin, "Systolic array implementation of multipliers for finite fields," IEEE Transaction on Circuit and Sy stems, Vol. 38, No. 7, pp. 796-800, July 1991.
    • (1991) IEEE Transaction on Circuit and Sy Stems , vol.38 , Issue.7 , pp. 796-800
    • Wang, C.L.1    Lin, J.L.2
  • 3
    • 0024768980 scopus 로고
    • Efficient bit-serial multiplication and the discrete-time Winer-Hopf equation over finite fields
    • Nov.
    • M. Morii, M. Kasahara, and D. Whiting, "Efficient bit-serial multiplication and the discrete-time Winer-Hopf equation over finite fields," IEEE Transactions on Information Theory, Vol. 35, No. 6, pp. 1177-1183, Nov. 1989.
    • (1989) IEEE Transactions on Information Theory , vol.35 , Issue.6 , pp. 1177-1183
    • Morii, M.1    Kasahara, M.2    Whiting, D.3
  • 7
    • 0027627109 scopus 로고
    • n multiplier structure: A structured design methodology
    • July
    • n multiplier structure: A structured design methodology," IEE Proc., Pt-E, Vol. 140, No. 4, pp. 185-190, July 1993.
    • (1993) IEE Proc., Pt-E , vol.140 , Issue.4 , pp. 185-190
    • Ibrahim, M.K.1
  • 9
    • 0029324353 scopus 로고
    • Bit-level systolic arrays for finite-field multiplication
    • C.W. Wu and M.K. Chang, "Bit-level systolic arrays for finite-field multiplication," Journal of VLSI Signal Processing, Vol. 10, pp. 85-92, 1995.
    • (1995) Journal of VLSI Signal Processing , vol.10 , pp. 85-92
    • Wu, C.W.1    Chang, M.K.2
  • 14
    • 0024105183 scopus 로고
    • Algorithms for multiplication in Galois field for implementation using systolic arrays
    • Nov.
    • S. Bandyopadhyay and A. Sengupta, "Algorithms for multiplication in Galois field for implementation using systolic arrays," IEE. Proc., Pt-E, Vol. 135, No. 6, pp. 336-339, Nov. 1988.
    • (1988) IEE. Proc., Pt-E , vol.135 , Issue.6 , pp. 336-339
    • Bandyopadhyay, S.1    Sengupta, A.2
  • 19
    • 0024029936 scopus 로고
    • A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases
    • June
    • I.S. Hsu, T.K. Truong, L.J. Deutsh, and I.S. Reed, "A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases," IEEE Transaction on Computers, Vol. 37, No. 6, pp. 735-739, June 1988.
    • (1988) IEEE Transaction on Computers , vol.37 , Issue.6 , pp. 735-739
    • Hsu, I.S.1    Truong, T.K.2    Deutsh, L.J.3    Reed, I.S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.